The 1:1 page table should be a 3 level PAE page table on x86-64
authorkaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk>
Mon, 11 Jul 2005 14:39:10 +0000 (14:39 +0000)
committerkaf24@firebug.cl.cam.ac.uk <kaf24@firebug.cl.cam.ac.uk>
Mon, 11 Jul 2005 14:39:10 +0000 (14:39 +0000)
commit8ff31ab726c3b2556d1e2dddd9206316b17b9be9
treeccd1c6117efbc707f844ed01836a47767ab0bf62
parent280cee75462987a5984628230dfbe7104a4bcf84
The 1:1 page table should be a 3 level PAE page table on x86-64

This is needed to support > 4GB machine physical addresses.

Signed-off-by: Chengyuan Li <chengyuan.li@intel.com>
Signed-off-by: Arun Sharma <arun.sharma@intel.com>
tools/libxc/xc_vmx_build.c
tools/python/xen/xend/image.py
xen/arch/x86/shadow32.c
xen/arch/x86/shadow_public.c
xen/arch/x86/vmx.c
xen/arch/x86/vmx_vmcs.c